1. Field of the Invention
The present invention relates to the field of high performance integrated circuit packaging.
2. Art Background
Traditionally, microprocessors have been packaged in ceramic pin grid array packages because of electrical and thermal performance requirements. More specifically, the high instruction execution speed of microprocessors places two limitations on the design of packaging for microprocessors. First, since power consumption is a function of the instruction execution speed and since microprocessors operate at high instruction execution speeds, the conservation of energy is one limitation placed on the design of packaging for microprocessors. Second, the high instruction execution speed of microprocessors requires the packaging to minimize the time for removing and supplying the transient power supply currents (e.g., the transient ground and the transient V.sub.CC supply currents) to the microprocessor die, in order to allow the circuit nodes to charge and discharge as quickly as possible.
The conservation of energy and time constraints can both be satisfied by providing the shortest paths from the printed circuit (PC) board to the die for the power supply signals (e.g. the ground supply signal and the V.sub.CC supply signal). In other words, energy is conserved by minimizing the distance that the power supply signals have to traverse from the PC board to the die, because the power supply signals encounter less obstructions (i.e., resistance and inductance) in the path. Furthermore, the time for supplying and removing the transient power supply currents from the PC board to the die is also minimized by minimizing the distance that the power supply signals have to traverse from the PC board to the die.
In the past, microprocessors have been packaged mostly in ceramic pin grid array packages, because the prior art solutions for shortening the power supply signal paths (from the PC board to the die) often cannot be successfully implemented in other types of packaging. One prior art method for shortening the power signal paths is the placement of capacitive electrical planes within the package. These capacitive electrical planes (which are also called thin layer capacitors) are connected to the power supply signals, and thus provide a local on-chip power source that can be quickly accessed by the die.
Unfortunately, capacitive electrical planes can only be implemented in a few types of materials. The feasibility of implementing capacitive electrical planes depends on the minimum separation distance that can be achieved between each power and ground plane and the dielectric constant of the package. Thus, since ceramic packages have high dielectric constants and provide for small separation distances, capacitive electrical planes can be implemented in ceramic packages. However, as mentioned above, capacitive electrical planes cannot be implemented in all types of packages. For example, the cheaper plastic package technology cannot use capacitive electrical planes to shorten the power supply signal paths, because plastic packages have a low dielectric constant and cannot provide small separation distances between adjacent electrical planes.
Another prior art solution for shortening the paths of the power supply signals is to mount chip capacitors on the package, and to couple these capacitors to the power supply signals so that these capacitors act as local sources of power. However, as the chip capacitors are expensive, this prior art solution increases the processing cost of the microprocessors.
Consequently, it would be desirable to provide a packaging method and apparatus for microprocessors that would cost effectively conserve energy and time in delivering the power supply signals from the PC board to the die. More specifically, a packaging method and apparatus for microprocessors is needed that would provide the shortest power signal paths from the PC board to the die without the use of capacitive electrical planes (which cannot be implemented in all types of packaging) and without the use of chip capacitors (which are expensive).